Practical and Profitable Alternatives to Greedy, Single-path Scheduling

Compiler writers continue to search for ways to use the ever-increasing number of parallel functional units in modern microarchitectures. The most popular approach today is to build a tracebased instruction scheduler, since they are effective and can be conceptually simple to implement. DAG-based schedulers that look along multiple control paths, instead of along just one as in a trace-based scheduler, have the potential to do better. This paper begins by presenting a DAG-based scheduler that is both conceptually simpler and easier to implement than previous approaches. A key component of this approach is the incorporation of redundancy elimination (RE) into the topdown scheduling algorithm. RE allows us to simplify the code motion process while still producing efficient instruction schedules. Our experimental results illustrate that our proposed DAG-based scheduler has concrete performance benefits over a superblock scheduler for programs with hardto-predict control flow. However, these results also expose problems that surface as both DAGbased and trace-based schedulers attempt to exploit even greater amounts of instruction-level parallelism (ILP). We find that these problems partially originate from the excessive greediness of topdown scheduling. In the second half of the paper, we show how to suppress the excessive greediness of top-down scheduling with bottom-up rescheduling. We develop bottom-up rescheduling algorithms for both the superblock and DAG-based approaches. Our experimental results with superblock scheduling show that bottom-up rescheduling effectively suppresses instruction overspeculation and register pressure while preserving the ILP exposed during top-down scheduling.